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IRQs support

Summary

Multiple Industry Standard Architecture (ISA) devices cannot share an ISA IRQ (except the serial ports); however, multiple PCI devices can share a PCI IRQ. On computers that use a PCI bus, the 16 standard IRQs can be programmed to either PCI or ISA mode. An IRQ cannot be programmed for both modes at once. IRQ assignment conflicts are analyzed and ways to solve then are discussed.

How IRQs are assigned to ISA devices in Oberon

IRQ Used by Module
0 (F) (S) System timer Kernel
1 (F) (S) Keyboard controller Input
2 (F) Programmable Interrupt Controller - remapped to IRQ9 Kernel
3 Normally COM2. Often shared with COM4. V24
4 Normally COM1. Often shared with COM3. V24
5 Spare. Normally LPT2.  
6 (F) Floppy disk controller Diskettes
7 Spare. Normally LPT1.  
8 (F) (S) System CMOS/real-time clock Kernel
9 (F) Spare  
10 Spare  
11 Spare  
12 (F) PS/2 mouse port Input
13 (F) (S) Spare on Pentium machines. For older processors: Floating point unit (FPU) 387 compatible Kernel
14 (D) Primary IDE controller ATADisks
15 (D) Secondary IDE controller ATADisks

(F) Fixed, hard-coded
(D) Dynamically evaluated by the system itself
ATADisks.Mod - confirmed in KernelLog
Adaptec7.Mod - confirmed in KernelLog
Net3Com509.Mod - confirmed in KernelLog
NetNe2000.Mod - not
UsbUhci.Mod - confirmed in KernelLog
Sound.Mod - not
(S) For system use only

IRQs communicated to the system via Oberon.Text:

The IRQ of a sound card must be specified in the Sound.Audio section. Preset to 7.
The IRQ of a Atapi CD-ROM must be specified in the Sound.CDAtapi section. Preset to 15.
The IRQ of a Mitsumi CD-ROM must be specified in the Sound.CDMitsumi section Preset to 10.

The IRQ assigned to PCI and AGP devices can be determined by executing the PCI analyzer command PCITools.Scan .

For a detailed discussion of the IRQs cfr. IRQ Details By Number.

How to avoid conflicting ISA IRQs

Here are some general ideas on how to allocate the limited number of IRQS.

For developers: How to control an IRQ by program

An interrupt handler is installed with the Kernel.InstallIP procedure and the interrupt is enabled by the Kernel. The procedure "p" must be defined as a normal "PROCEDURE p;". On entry to p, interrupts are disabled and may be enabled with SYSTEM.STI(). At exit from p, the state of interrupts are restored. The acknowledgement of a hardware interrupt is done by the Kernel. No end-of-interrupt has to be signalled explicitly in procedure p. IRQs are mapped starting at interrupt Kernel.IRQ.

At entry to procedure p the stack is as follows:

    56    EFLAGS'' 
    52    CS'' 
    48    EIP''    (IRETD from glue code) 
    44    errorcode 
    40    intnum 
    36    EAX 
    32    ECX 
    28    EDX 
    24    EBX 
    20    ESP'    (overwritten) 
    16    EBP 
    12    ESI 
    08    EDI 
    04    EIP'    (RET from p) 
    00    EBP'    <-- EBP 
    xx    locals    <-- ESP
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